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1 of 15 011800 features 8051-compatible microcontroller for secure/sensitive applications - 32, 64, or 128 kbytes of nonvolatile sram for program and/or data storage - in-system programming via on-chip serial port - capable of modifying its own program or data memory in the end system firmware security features: - memory stored in encrypted form - encryption using on-chip 64-bit key - automatic true random key generator - sdi (self-destruct input) - improved security over previous generations - protects memory contents from piracy crashproof operation - maintains all nonvolatile resources for over 10 years in the absence of power - power-fail reset - early warning power-fail interrupt - watchdog timer - precision reference for power monitor fully 8051-compatible - 128 bytes scratchpad ram - two timer/counters - on-chip serial port - 32 parallel i/o port pins permanently powered real time clock package outline description the ds2252t secure microcontroller module is an 8051-compatible microcontroller based on nonvolatile ram technology. it is designed for systems that need to protect memory contents from disclosure. this includes key data, sensitive algorithms, and proprietary information of all types. like other members of the secure microcontroller family, it provides full compatibility with the 8051 instruction set, timers, serial port, and parallel i/o ports. by using nv ram instead of rom, the user can program, then reprogram the microcontroller while in-system. this allows frequent changing of sensitive processes with minimal effort. the ds2252t provides an array of mechanisms to prevent an attacker from examining the memory. it is designed to resist all levels of threat including observation, analysis, and physical attack. as a result, a massive effort would be required to obtain any information about ds2252t secure microcontroller module www.dalsemi.com 1202140 40-pin simm
ds2252t 2 of 15 memory contents. furthermore, the ?soft? nature of the ds2252t allows frequent modification of secure information. this minimizes that value of any information that is obtained. using a security system based on the ds5002fp, the ds2252t protects the memory contents from disclosure. it loads program memory via its serial port and encrypts it in real time prior to storing it in sram. once encrypted, the ram contents and the program flow are unintelligible. the real data exists only inside the processor chip after being decrypted. any attempt to discover the on-chip data, encryption keys, etc., results in its destruction. extensive use of nonvolatile lithium-backed technology creates a microcontroller that retains data for over 10 years at room temperature, but which can be erased instantly if tampered with. the ds2252t even interfaces directly to external tamper protection hardware. the ds2252t provides a permanently powered real time lock with interrupts for time stamp and date. it keeps time to one hundredth of a second using its onboard 32 khz crystal. like other secure microcontrollers in the family, the ds2252t provides crashproof operation in portable systems or systems with unreliable power. these features include the ability to save the operating state, power-fail reset, power-fail interrupt, and watchdog timer. all nonvolatile memory and resources are maintained for over 10 years at room temperature in the absence of power. a user loads programs into the ds2252t via its on-chip serial bootstrap loader. this function supervises the loading of software into nv ram, validates it, then becomes transparent to the user. it also manages the loading of new encryption keys automatically. software is stored in onboard cmos sram. using its internal partitioning, the ds2252t can divide a common ram into user selectable program and data segments. this partition can be selected at program loading time, but can be modified anytime later. the microcontroller will decode memory access to the sram, access memory via its byte- wide bus and write-protect the memory portion designated as program (rom). a detailed summary of the security features is provided in the user?s guide section of the secure microcontroller data book. an overview is also available in the ds5002fp data sheet.
ds2252t 3 of 15 ds2252t block diagram figure 1
ds2252t 4 of 15 pin assignment 1 p1.0 11 p1.5 21 p3.1 txd 31 p3.6 wr 2v cc 12 p0.4 22 ale 32 p2.4 3 p1.1 13 p1.6 23 p3.2 int0 33 p3.7 rd 4 p0.0 14 p0.5 24 prog 34 p2.3 5 p1.2 15 p1.7 25 p3.3 int1 35 xtal2 6 p0.1 16 p0.6 26 p2.7 36 p2.2 7 p1.3 17 rst 27 p3.4 t0 37 xtal1 8 p0.2 18 p0.7 28 p2.6 38 p2.1 9 p1.4 19 p3.0 rxd 29 p3.5 t1 39 gnd 10 p0.3 20 sdi 30 p2.5 40 p2.0 pin description pin description 4, 6, 8, 10, 12, 14, 16, 18 p0.0 - p0.7. general purpose i/o port 0. this port is open-drain and can not drive a logic 1. it requires external pullups. port 0 is also the multiplexed expanded address/data bus. when used in this mode, it does not require pullups. 1, 3, 5, 7, 9, 11, 13, 15 p1.0 - p1.7. general purpose i/o port 1. 40, 38, 36, 34, 32, 30, 28, 26 p2.0 - p2.7. general purpose i/o port 2. also serves as the msb of the expanded address bus. 19 p3.0 rxd. general purpose i/o port pin 3.0. also serves as the receive signal for the on board uart. this pin should not be connected directly to a pc com port. 21 p3.1 txd. general purpose i/o port pin 3.1. also serves as the transmit signal for the on board uart. this pin should not be connected directly to a pc com port. 23 p3.2 int0 . general purpose i/o port pin 3.2. also serves as the active low external interrupt 0. this pin is also connected to the intp output of the ds1283 real time clock. 25 p3.3 int1 . general purpose i/o port pin 3.3. also serves as the active low external interrupt 1. 27 p3.4 t0. general purpose i/o port pin 3.4. also serves as the timer 0 input. 29 p3.5 t1. general purpose i/o port pin 3.5. also serves as the timer 1 input. 31 p3.6 wr . general purpose i/o port pin. also serves as the write strobe for expanded bus operation. 33 p3.7 rd . general purpose i/o port pin. also serves as the read strobe for expanded bus operation. 17 rst - active high reset input. a logic 1 applied to this pin will activate a reset state. this pin is pulled down internally, can be left unconnected if not used. an rc power-on reset circuit is not needed and is not recommended.
ds2252t 5 of 15 pin description 22 ale - address latch enable. used to de-multiplex the multiplexed expanded address/data bus on port 0. this pin is normally connected to the clock input on a ?373 type transparent latch. 35, 37 xtal2, xtal1. used to connect an external crystal to the internal oscillator. xtal1 is the input to an inverting amplifier and xtal2 is the output. 39 gnd - logic ground. 2 v cc - +5v . 24 prog - invokes the bootstrap loader on a falling edge. this signal should be debounced so that only one edge is detected. if connected to ground, the microcontroller will enter bootstrap loading on power up. this signal is pulled up internally. 20 sdi ? self-destruct input. a logic 1 applied to this input causes a hardware unlock. this involves the destruction of encryption keys, vector ram, and the momentary removal of power from v cco . this pin should be grounded if not used. instruction set the ds2252t executes an instruction set that is object code-compatible with the industry standard 8051 microcontroller. as a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the ds2252t. a complete description of the instruction set and operation are provided in the user?s guide section of the secure microcontroller data book. memory organization figure 2 illustrates the memory map accessed by the ds2252t. the entire 64k of program and 64k of data are available to the byte-wide bus. this preserves the i/o ports for application use. an alternate configuration allows dynamic partitioning of a 64k space as shown in figure 3. any data area not mapped into the nv ram is reached via the expanded bus on ports 0 and 2. off-board program memory is not available for security reasons. selecting pes=1 provides access to the real time clock as shown in figure 4. these selections are made using special function registers. the memory map and its controls are covered in detail in the user?s guide section of the secure microcontroller data book.
ds2252t 6 of 15 ds2252t memory map in non-partitionable mode (pm=1) figure 2 ds2252t memory map in partitionable (pm=0) figure 3 nv ram program nv ram data program memory data memory ( movx ) ffffh -- 0000h -- -- 64k nv ram program nv ram data program memory data memory ( movx ) ffffh -- 0000h -- partition note: partitionable mode is not supported on the 128kb version of the ds2252t. legend: = nv ram memory = expanded bus ( ports 0 and 2 ) = not available
ds2252t 7 of 15 ds2252t memory map with (pes=1) figure 4 power management the ds2252t monitors v cc to provide power-fail reset, early warning power-fail interrupt, and switch- over to lithium backup. it uses an internal band-gap reference in determining the switch points. these are called v pfw , v ccmin , and v li respectively. when v cc drops below v pfw , the ds2252t will perform an interrupt vector to location 2bh if the power-fail warning is enabled. full processor operation continues regardless. when power falls further to v ccmin , the ds2252t invokes a reset state. no further code execution will be performed unless power rises back above v ccmin . all decoded chip enables and the r/ w signal go to an inactive (logic 1) state. v cc is still the power source at this time. when v cc drops further to below v li , internal circuitry will switch to the built-in lithium cell for power. the majority of internal circuits will be disabled and the remaining nonvolatile states will be retained. the user?s guide has more information on this topic. the trip points v ccmin and v pfw are listed in the electrical specifications. nv ram program program memory data memory ( movx ) ffffh -- 0000h -- partition = not accessible real-time cloc k c000h -- b000h -- 4000h -- -- 64k -- 16k
ds2252t 8 of 15 absolute maximum ratings* voltage on any pin relative to ground -0.3v to (v cc + 0.5v) voltage on v cc relative to ground -0.3v to +6.0v operating temperature 2 -40c to +85c storage temperature -55c to +125c soldering temperature 260c for 10 seconds 1 this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 2 storage temperature is defined as the temperature of the device when v cc =0v and v li =0v. in this state the contents of sram are not battery-backed and are undefined. dc characteristics (t a =0c to 70c; v cc =5v 10%) parameter symbol min typ max units notes input low voltage v il -0.3 +0.8 v 1 input high voltage v ih1 2.0 v cc +0.3 v 1 input high voltage (rst, xtal1, prog ) v ih2 3.5 v cc +0.3 v 1 output low voltage @ i ol =1.6 ma (ports 1, 2, 3) v ol1 0.15 0.45 v 1 output low voltage @ i ol =3.2 ma (ports 0, ale) v ol2 0.15 0.45 v 1 output high voltage @ i oh = -80 a (ports 1, 2, 3) v oh1 2.4 4.8 v 1 output high voltage @ i oh =-400 a (ports 0, ale) v oh2 2.4 4.8 v 1 input low current v in = 0.45v (ports 1, 2, 3) i il -50 a transition current; 1 to 0 v in = 2.0v (ports 1, 2, 3) i tl -500 a input leakage current 0.45 < v in < v cc (port 0) i il 10 a rst pulldown resistor r re 40 150 k ? power fail warning voltage v prw 4.25 4.37 4.50 v 1 minimum operating voltage v ccmin 4.00 4.12 4.25 v 1 operating current @ 16 mhz i cc 45 ma 4 idle mode current @ 12 mhz i idle 7.0 ma 5 stop mode current i stop 80 a 6 pin capacitance c in 10 pf 7
ds2252t 9 of 15 dc characteristics (continued) (t a =0c to 70c; v cc =5v 10%) reset trip point in stop mode w/bat=3.0v w/bat=3.3v 4.0 4.4 4.25 4.65 v1 sdi input high voltage v ihs 2.0 v cc v 1, 2 sdi input high voltage v ihs 2.0 3.5 v 1, 2 sdi pulldown resistor r sdi 25 60 k ? ac characteristics (t a =0c to 70c; v cc =0v to 5v) parameter symbol min typ max units notes sdi pulse reject (4.5v < v cc < 5.5v) (v cc =0v, v bat =2.9v) t spr 2 4 s 10 sdi pulse accept (4.5v < v cc < 5.5v) (v cc =0v, v bat =2.9v) t spa 10 50 s 10
ds2252t 10 of 15 ac characteristics: expanded bus mode timing specifications (t a =0c to70c; v cc =5v 10%) # parameter symbol min max units 1 oscillator frequency 1/t clk 1.0 16 (-16) mhz 2 ale pulse width t alpw 2t clk -40 ns 3 address valid to ale low t avall t clk -40 ns 4 address hold after ale low t avaav t clk -35 ns 14 rd pulse width t rdpw 6t clk -100 ns 15 wr pulse width t wrpw 6t clk -100 ns 16 rd low to valid data in @ 12 mhz @ 16 mhz t rdldv 5t clk -165 5t clk -105 ns ns 17 data hold after rd high t rdhdv 0ns 18 data float after rd high t rdhdz 2t clk -70 ns 19 ale low to valid data in @ 12 mhz @ 16 mhz t allvd 8 clk -150 8t clk -90 ns ns 20 valid addr. to valid data in @ 12 mhz @ 16 mhz t avdv 9t clk -165 9t clk -105 ns ns 21 ale low to rd or wr low t allrdl 3t clk -50 3t clk +50 ns 22 address valid to rd or wr low t avrdl 4t clk -130 ns 23 data valid to wr going low t dvwrl t clk -60 ns 24 data valid to wr high @ 12 mhz @ 16 mhz t dvwrh 7t clk -150 7t clk -90 ns ns 25 data valid after wr high t wrhdv t clk -50 ns 26 rd low to address float t rdlaz 0ns 27 rd or wr high to ale high t rdhalh t clk -40 t clk +50 ns expanded data memory read cycle
ds2252t 11 of 15 expanded data memory write cycle ac characteristics (continued) external clock drive (t a =0c to70c; v cc =5v 10%) # parameter symbol min max units 28 external clock high time @ 12 mhz @ 16 mhz t clkhpw 20 15 ns ns 29 external clock low time @ 12 mhz @ 16 mhz t clklpw 20 15 ns ns 30 external clock rise time @ 12 mhz @ 16 mhz t clkr 20 15 ns ns 31 external clock fall time @ 12 mhz @ 16 mhz t clkf 20 15 ns ns external clock timing
ds2252t 12 of 15 ac characteristics (continued) power cycling timing (t a =0c to70c; v cc =5v 10%) # parameter symbol min max units 32 slew rate from v ccmin to 3.3v t f 130 s 33 crystal start-up time t csu (note 8) 34 power-on reset delay t por 21504 t clk power cycle timing ac characteristics (cont'd) serial port timing - mode 0 (t a =0c to70c; v cc =5v 10%) # parameter symbol min max units 35 serial port clock cycle time t spclk 12t clk s 36 output data setup to rising clock edge t doch 10t clk -133 ns 37 output data hold after rising clock edge t chdo 2t clk -117 ns 38 clock rising edge to input data valid t chdv 10t clk -133 ns 39 input data hold after rising clock edge t chdiv 0ns
ds2252t 13 of 15 serial port timing - mode 0 notes: 1. all voltage referenced to ground. 2. sdi should be taken to a logic high when v cc =+5v, and to approximately 3v when v cc <3v. 3. sdi is deglitched to prevent accidental destruction. the pulse must be longer than t spr to pass the deglitcher, but sdi is not guaranteed unless it is longer than t spa . 4. maximum operating i cc is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf =10 ns, v il = 0.5v; xtal2 disconnected; rst = port0 = v cc . 5. idle mode i idle is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf = 10 ns, v il = 0.5v; xtal2 disconnected; port0 = v cc , rst = v ss . 6. stop mode i stop is measured with all output pins disconnected; port0 = v cc ; xtal2 not connected; rst = xtal1 = v ss . 7. pin capacitance is measured with a test frequency - 1 mhz, t a = 25c. 8. crystal start-up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. the user should check with the crystal vendor for a worst case specification on this time.
ds2252t 14 of 15 package drawing pkg inches dim min max a 2.645 2.655 b 2.379 2.389 c 0.995 1.005 d 0.395 0.405 e 0.245 0.255 f 0.050 bsc g 0.075 0.085 h 0.245 0.255 i 0.950 bsc j 0.120 0.130 k 1.320 1.330 l 1.445 1.455 m 0.057 0.067 n - 0.300 o - 0.165 p 0.047 0.054
15 of 15 data sheet revision summary the following represent the key differences between 12/13/95 and 08/16/96 version of the ds2252t data sheet. please review this summary carefully. 1. change v cc slew rate specification to reference 3.3v instead of v li . 2. add minimum value to pcb thickness. the following represent the key differences between 08/16/96 and 05/28/97 version of the ds2252t data sheet. please review this summary carefully. 1. ac characteristics for battery-backed sdi pulse specification added. the following represent the key differences between 05/28/97 and 11/08/99 version of the ds2252t data sheet. please review this summary carefully. (pcn i80903) 1. correct absolute maximum ratings to reflect changes to ds5002fp microprocessor. 2. add note clarifying that sram contents are not defined under storage temperature conditions. the following represent the key differences between 11/08/99 and 01/18/00 version of the ds2252t data sheet. please review this summary carefully. 1. datasheet conversion from interleaf to word.

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